SH7206 Datasheet, PDF (166/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Interrupt Controller (INTC)
5.6.2 Stack after Interrupt Exception Handling
Figure 5.3 shows the stack after interrupt exception handling.
Address
4n – 8 PC*¹
4n – 4 SR
4n
32 bits
32 bits
SP*²
Notes: 1. PC: Start address of the next instruction (return destination instruction)
after the executed instruction
2. Always make sure that SP is a multiple of 4.
Figure 5.3 Stack after Interrupt Exception Handling
Rev. 3.00 Jun. 18, 2008 Page 142 of 1160
REJ09B0191-0300