SH7206 Datasheet, PDF (991/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 I/O Ports
20.6.2 Port E Data Registers H, L (PEDRH, PEDRL)
PEDRH and PEDRL are 16-bit readable/writable registers that store port E data. Bits PE16DR to
PE0DR correspond to pins PE16/CS8 to PE0/TIOC0A/DREQ0, respectively.
When a pin function is general output, if a value is written to PEDRH or PEDRL, that value is
output directly from the pin, and if PEDRH or PEDRL is read, the register value is returned
directly regardless of the pin state.
When a pin function is general input, if PEDRH or PEDRL is read, the pin state, not the register
value, is returned directly. If a value is written to PEDRH or PEDRL, although that value is
written into PEDRH or PEDRL, it does not affect the pin state. Table 20.10 summarizes PEDRH
and PEDRL read/write operations.
PEDRH and PEDRL are initialized to the respective values shown in table 20.9 by a power-on
reset. PEDRH and PEDRL are not initialized by a manual reset or in sleep mode or software
standby mode.
(1) Port E Data Register H (PEDRH)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PE16
DR
Initial value: 0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit
15 to 6
Initial
Bit Name Value

All 0
5 to 1 
All 1
0
PE16DR 0
R/W
R
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Reserved
These bits are always read as 1. The write value should
always be 1.
See table 20.10
Rev. 3.00 Jun. 18, 2008 Page 967 of 1160
REJ09B0191-0300