SH7206 Datasheet, PDF (245/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Bit
5 to 2
1, 0
Section 8 Bus State Controller (BSC)
Bit Name

Initial
Value
All 0
HW[1:0] 00
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Delay Cycles from RD, WEn Negation to Address, CSn
Negation
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 3.00 Jun. 18, 2008 Page 221 of 1160
REJ09B0191-0300