SH7206 Datasheet, PDF (178/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Interrupt Controller (INTC)
5.9 Data Transfer with Interrupt Request Signals
Interrupt request signals can be used to activate the DMAC and transfer data.
Interrupt sources that are designated to activate the DMAC are masked without being input to the
INTC. The mask condition is as follows:
Mask condition = DME • (DE0 • interrupt source select 0 + DE1 • interrupt source select 1
+ DE2 • interrupt source select 2 + DE3 • interrupt source select 3 +
DE4 • interrupt source select 4 + DE5 • interrupt source select 5 + DE6
• interrupt source select 6 + DE7 • interrupt source select 7)
Figure 5.13 shows a block diagram of interrupt control.
Here, DME is bit 0 in DMAOR of the DMAC, and DEn (n = 0 to 7) is bit 0 in CHCR0 to CHCR7
of the DMAC. For details, see section 9, Direct Memory Access Controller (DMAC).
Interrupt source
Interrupt source
flag clearing
(by DMAC)
DMAC
Interrupt source (not specified as DMAC activating source)
INTC
CPU interrupt request
CPU
Figure 5.13 Interrupt Control Block Diagram
Rev. 3.00 Jun. 18, 2008 Page 154 of 1160
REJ09B0191-0300