SH7206 Datasheet, PDF (524/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
1
SCC
0
R/(W) Synchronous Clearing Control
Specifies whether to clear TCNT_3 and TCNT_4 in the
MTU2S when synchronous counter clearing between
the MTU2 and MTU2S occurs in complementary PWM
mode.
When using this control, place the MTU2S in
complementary PWM mode.
When modifying the SCC bit while the counters are
operating, do not modify the CCE or WRE bits.
Counter clearing synchronized with the MTU2 is
disabled by the SCC bit setting only when synchronous
clearing occurs outside the Tb interval at the trough.
When synchronous clearing occurs in the Tb interval at
the trough including the period immediately after
TCNT_3 and TCNT_4 start operation, TCNT_3 and
TCNT_4 in the MTU2S are cleared.
For the Tb interval at the trough in complementary
PWM mode, see figure 10.40.
In the MTU2, this bit is reserved. It is always read as 0
and the write value should always be 0.
0: Enables clearing of TCNT_3 and TCNT_4 in the
MTU2S by MTU2–MTU2S synchronous clearing
operation
1: Disables clearing of TCNT_3 and TCNT_4 in the
MTU2S by MTU2–MTU2S synchronous clearing
operation
[Setting condition]
• When 1 is written to SCC after reading SCC = 0
Rev. 3.00 Jun. 18, 2008 Page 500 of 1160
REJ09B0191-0300