SH7206 Datasheet, PDF (1184/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Types of exception handling and priority
order.......................................................... 87
U
UBC trigger timing............................... 1115
Unconditional branch instructions with
no delay slot.............................................. 37
User break controller (UBC) .................. 157
User break interrupt ................................ 127
Using interval timer mode ...................... 724
Using watchdog timer mode................... 722
V
Vector base register (VBR)....................... 31
W
Wait between access cycles .................... 343
Watchdog timer (WDT).......................... 711
Watchdog timer timing ......................... 1118
Write-back buffer
(only for operand cache) ......................... 191
Rev. 3.00 Jun. 18, 2008 Page 1160 of 1160
REJ09B0191-0300