SH7206 Datasheet, PDF (127/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Exception Handling
4.6 Exceptions Triggered by Instructions
4.6.1 Types of Exceptions Triggered by Instructions
Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal
instructions, and integer division exceptions, as shown in table 4.10.
Table 4.10 Types of Exceptions Triggered by Instructions
Type
Trap instruction
Slot illegal
instructions
General illegal
instructions
Integer division
exceptions
Source Instruction
Comment
TRAPA
Undefined code placed
immediately after a delayed
branch instruction (delay slot),
instructions that rewrite the PC,
32-bit instructions, RESBANK
instruction, DIVS instruction, and
DIVU instruction
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N
32-bit instructions: BAND.B, BANDNOT.B,
BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B,
MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S,
MOVU.B, MOVU.W.
Undefined code anywhere
besides in a delay slot
Division by zero
DIVU, DIVS
Negative maximum value ÷ (−1) DIVS
Rev. 3.00 Jun. 18, 2008 Page 103 of 1160
REJ09B0191-0300