SH7206 Datasheet, PDF (1124/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 Electrical Characteristics
CKIO
A25 to A0
A12/A11^*1
Td1
Td2
Td3
Td4
Tr
Tc1
Tc2
Tc3
Tc4
Tde
t_AD1
t_AD1
Row
address
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
Column
address
READ command
t_AD1
t_AD1
CSn
RD/WR
RASU/L
CASU/L
DQMxx
t_CSD1
t_RWD1
t_RASD1
t_RASD1
t_CASD1
t_DQMD1
D31 to D0
t_BSD
BS
t_CSD1
tRWD1
t_CASD1
t_DQMD1
t_RDS2
t_RDH2
t_BSD
t_RDS2
t_RDH2
CKE
DACKn
TENDn*²
t_DACD
(High)
t_DACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 25.29 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: ACT + READ Commands, CAS Latency 2, WTRCD = 0 Cycle)
Rev. 3.00 Jun. 18, 2008 Page 1100 of 1160
REJ09B0191-0300