SH7206 Datasheet, PDF (288/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
8.5 Operation
8.5.1 Endian/Access Size and Data Alignment
This LSI supports big endian, in which the 0 address is the most significant byte (MSB) in the byte
data.
Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and SRAM
with byte selection. Two data bus widths (16 bits and 32 bits) are available for SDRAM. Two data
bus widths (8 bits and 16 bits) are available for PCMCIA interface. For MPX-I/O, the data bus
width is fixed at 8 bits or 16 bits, or 8 bits or 16 bits can be selected by the access address. The
data bus width for burst MPX-I/O is fixed at 32 bits. Data alignment is performed in accordance
with the data bus width of the device. This also means that when longword data is read from a
byte-width device, the read operation must be done four times. In this LSI, data alignment and
conversion of data length is performed automatically between the respective interfaces.
Tables 8.5 to 8.7 show the relationship between device data width and access unit.
Table 8.5 32-Bit External Device Access and Data Alignment
Operation
D31 to
D24
Byte access Data
at 0
7 to 0
Byte access 
at 1
Byte access 
at 2
Byte access 
at 3
Word access Data
at 0
15 to 8
Word access 
at 2
Longword Data
access at 0 31 to 24
Data Bus
D23 to
D16
D15 to
D8


Data
7 to 0



Data
7 to 0

Data
7 to 0

Data
23 to 16

Data
15 to 8
Data
15 to 8
WE3,
D7 to D0 DQMUU

Assert




Data
7 to 0


Assert
Data
7 to 0
Data
7 to 0

Assert
Strobe Signals
WE2,
DQMUL
WE1,
DQMLU


Assert


Assert


Assert


Assert
Assert
Assert
WE0,
DQMLL



Assert

Assert
Assert
Rev. 3.00 Jun. 18, 2008 Page 264 of 1160
REJ09B0191-0300