SH7206 Datasheet, PDF (254/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
1, 0
HW[1:0] 00
R/W Delay Cycles from RD, WEn Negation to Address,
CS5 Negation
Specify the number of delay cycles from RD and WEn
negation to address and CS5 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 3.00 Jun. 18, 2008 Page 230 of 1160
REJ09B0191-0300