SH7206 Datasheet, PDF (1027/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 High-Performance User Debugging Interface (H-UDI)
TCK
TDO
(after execution of TDO change
timing switch command)
TDO
(initial value)
t_TDOD
t_TDOD
Figure 23.3 H-UDI Data Transfer Timing
23.4.4 H-UDI Reset
An H-UDI reset is executed by setting an H-UDI reset assert command in SDIR. An H-UDI reset
is of the same kind as a power-on reset. An H-UDI reset is released by setting an H-UDI reset
negate command. The required time between the H-UDI reset assert command and H-UDI reset
negate command is the same as time for keeping the RES pin low to apply a power-on reset.
SDIR
H-UDI reset assert
H-UDI reset negate
Chip internal reset
CPU state
Fetch the initial values of PC and SR from
the exception handling vector table
Figure 23.4 H-UDI Reset
23.4.5 H-UDI Interrupt
The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in
SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in fetching the
exception service routine start address from the exception handling vector table, jumping to that
address, and starting program execution from that address. This interrupt request has a fixed
priority level of 15.
H-UDI interrupts are accepted in sleep mode, but not in software standby mode.
Rev. 3.00 Jun. 18, 2008 Page 1003 of 1160
REJ09B0191-0300