SH7206 Datasheet, PDF (504/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.3.18 Timer Read/Write Enable Register (TRWER)
TRWER is an 8-bit readable/writable register that enables or disables access to the registers and
counters which have write-protection capability against accidental modification in channels 3 and
4.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
-
- RWE
Initial value: 0
0
0
0
0
0
0
1
R/W: R
R
R
R
R
R
R R/W
Bit
Bit Name
7 to 1 —
0
RWE
Initial
Value
All 0
1
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Read/Write Enable
Enables or disables access to the registers which have
write-protection capability against accidental
modification.
0: Disables read/write access to the registers
1: Enables read/write access to the registers
[Clearing condition]
• When 0 is written to the RWE bit after reading
RWE = 1
• Registers and counters having write-protection capability against accidental modification
22 registers: TCR_3, TCR_4, TMDR_3, TMDR_4, TIORH_3, TIORH_4, TIORL_3,
TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1,
TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT4.
Rev. 3.00 Jun. 18, 2008 Page 480 of 1160
REJ09B0191-0300