SH7206 Datasheet, PDF (1134/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 Electrical Characteristics
CKIO
A25 to A0
A12/A11^*1
CSn
RD/WR
RASU/L
CASU/L
DQMxx
Tp
Tpw
Trr
t_AD3
t_AD3
t_AD3
t_AD3
t_CSD2
t_CSD2
t_CSD2
t_CSD2
t_RWD2
t_RWD2
t_RASD2
t_RASD2
t_RASD2
t_RASD2
t_CASD2
t_CASD2
t_CASD2
t_DQMD2
D31 to D0
(Hi-Z)
Trc
Trc
Trc
BS
CKE
DACKn
TENDn ^*2
t_CKED2
t_CKED2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 25.39 Synchronous DRAM Self-Refreshing Timing in Low-Frequency Mode
(WTRP = 2 Cycles)
Rev. 3.00 Jun. 18, 2008 Page 1110 of 1160
REJ09B0191-0300