SH7206 Datasheet, PDF (381/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Direct Memory Access Controller (DMAC)
Section 9 Direct Memory Access Controller (DMAC)
The DMAC can be used in place of the CPU to perform high-speed transfers between external
devices that have DACK (transfer request acknowledge signal), external memory, on-chip
memory, memory-mapped external devices, and on-chip peripheral modules.
9.1 Features
• Number of channels: Eight channels (channels 0 to 7) selectable
Four channels (channels 0 to 3) can receive external requests.
• 4-Gbyte physical address space
• Data transfer unit is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes
(longword × 4)
• Maximum transfer count: 16,777,216 transfers (24 bits)
• Address mode: Dual address mode and single address mode are supported.
• Transfer requests
 External request
 On-chip peripheral module request
 Auto request
The following modules can issue on-chip peripheral module requests.
 Eight SCIF sources, two IIC3 sources, two A/D converter sources, five MTU2 sources, and
two CMT sources
• Selectable bus modes
 Cycle steal mode (normal mode and intermittent mode)
 Burst mode
• Selectable channel priority levels: The channel priority levels are selectable between fixed
mode and round-robin mode.
• Interrupt request: An interrupt request can be sent to the CPU on completion of half- or full-
data transfer. Through the HE and HIE bits in CHCR, an interrupt is specified to be issued to
the CPU when half of the initially specified DMA transfer is completed.
• External request detection: There are following four types of DREQ input detection.
 Low level detection
 High level detection
 Rising edge detection
 Falling edge detection
Rev. 3.00 Jun. 18, 2008 Page 357 of 1160
REJ09B0191-0300