SH7206 Datasheet, PDF (31/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

1.2 Block Diagram
Section 1 Overview
SH-2A
CPU core
CPU instruction fetch bus (F bus)
CPU bus
(C bus)
CPU memory access bus (M bus) _{(I clock)}
Cache
controller
Instruction
cache memory
8 Kbytes
Operand
cache memory
8 Kbytes
On-chip RAM
128 Kbytes
User break
controller
(UBC)
UBCTRG output
Internal bus (I bus) (B clock)
Bus state
controller
(BSC)
Port
External bus input/output
External bus width mode input
Peripheral
bus controller
Direct memory
access controller
(DMAC)
DREQ input
DACK output
TEND output
Peripheral bus (P clock)
Pin function
controller
(PFC)
I/O ports
Clock pulse
generator (CPG)
Interrupt
controller
(INTC)
Multi-function
timer pulse
unit 2
(MTU2)
Multi-function
timer pulse
unit 2
subset
(MTU2S)
Port output
enable 2
(POE2)
Compare
match timer
(CMT)
Port
Port
Port
General input/output EXTAL input,
XTAL output,
CKIO input/output,
Clock mode input
RES input,
MRES input,
NMI input,
IRQ input,
PINT input,
IRQOUT output
Port
Timer pulse
input/output
Port
Timer pulse
input/output
Port
POE input
High-performance
user debugging
interface
(H-UDI)
Power-down
mode
control
Port
JTAG input/output
D/A converter
(DAC)
A/D converter
(ADC)
I²C bus
interface 3
(IIC3)
Serial
communication
interface
with FIFO
(SCIF)
Watchdog
timer
(WDT)
Port
Analog output
Port
Analog input,
ADTRG input
Port
I²C bus
input/output
Figure 1.1 Block Diagram
Port
Serial input/output
Port
WDTOVF output
Rev. 3.00 Jun. 18, 2008 Page 7 of 1160
REJ09B0191-0300