SH7206 Datasheet, PDF (767/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
6
TEND
1
R/(W)* Transmit End
Indicates that when the last bit of a serial character
was transmitted, SCFTDR did not contain valid data,
so transmission has ended.
0: Transmission is in progress
[Clearing condition]
• TEND is cleared to 0 when 0 is written after 1 is
read from TEND after transmit data is written in
SCFTDR*¹
1: End of transmission
[Setting conditions]
• TEND is set to 1 when the chip is a power-on
reset
• TEND is set to 1 when TE is cleared to 0 in the
serial control register (SCSCR)
• TEND is set to 1 when SCFTDR does not contain
receive data when the last bit of a one-byte serial
character is transmitted
Note: 1. Do not use this bit as a transmit end flag
when the DMAC writes data to SCFTDR
due to a TXI interrupt request.
Rev. 3.00 Jun. 18, 2008 Page 743 of 1160
REJ09B0191-0300