SH7206 Datasheet, PDF (750/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 14 Watchdog Timer (WDT)
14.5.4 System Reset by WDTOVF Signal
If the WDTOVF signal is input to the RES pin of this LSI, this LSI cannot be initialized correctly.
Avoid input of the WDTOVF signal to the RES pin of this LSI through glue logic circuits. To
reset the entire system with the WDTOVF signal, use the circuit shown in figure 14.6.
Reset input
(Low active)
Reset signal to
entire system
(Low active)
RES
WDTOVF
Figure 14.6 Example of System Reset Circuit Using WDTOVF Signal
14.5.5 Manual Reset in Watchdog Timer Mode
When a manual reset occurs in watchdog timer mode, the bus cycle is continued. If a manual reset
occurs while the bus is released or during DMAC burst transfer, manual reset exception handling
will be pended until the CPU acquires the bus mastership.
However, if the duration from generation of the manual reset to the bus cycle end is equal to or
longer than the duration of the internal manual reset activated, the occurrence of the internal
manual reset source is ignored instead of being pended, and the manual reset exception handling is
not executed.
Rev. 3.00 Jun. 18, 2008 Page 726 of 1160
REJ09B0191-0300