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SH7206 Datasheet, PDF (878/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series | |||
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Section 17 A/D Converter (ADC)
(1)
PÏ
Address
(2)
Write
signal
Input sampling
timing
ADIF
tD
tSPL
tCONV
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
tD: A/D conversion start delay time
tSPL: Input sampling time
tCONV: A/D conversion time
Figure 17.5 A/D Conversion Timing
Table 17.4 A/D Conversion Time (Single Mode)
CKS[1] = 0
CKS[0] = 0
CKS[0] = 1
Item
Symbol Min. Typ. Max. Min. Typ. Max.
A/D conversion tD
start delay time
11
â
14
19
â
26
Input sampling
tSPL
time
â
33
â
â
65
â
A/D conversion tCONV
time
135 â
138 267 â
274
Note: Values in the table are the numbers of states.
CKS[1] = 1
CKS[0] = 0
Min. Typ. Max.
35
â
50
â
129 â
531 â
546
Rev. 3.00 Jun. 18, 2008 Page 854 of 1160
REJ09B0191-0300
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