SH7206 Datasheet, PDF (217/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Cache
Cache
Hit/
CPU Cycle Miss
Write-Back Mode/
Write-Through U
Mode
Bit
External Memory
Accession
(through Internal Bus)
Cache Contents
Operand
cache
Write
Hit
Write-through
 Write cycle CPU issues is Renewed to new values by write
mode
generated.
cycle the CPU issues
Write-back mode x Not generated
Renewed to new values by write
cycle the CPU issues
Miss
Write-through
mode
 Write cycle CPU issues is
generated.
Not renewed*
Write-back mode 0
Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle.
Subsequently renewed again to
new values in write cycle CPU
issues.
1 Cache renewal cycle is
Renewed to new values by
generated. Succeedingly
cache renewal cycle.
write-back cycle in write-back Subsequently renewed again to
buffer is generated.
new values in write cycle CPU
issues.
[Legend]
x:
Don't care.
Notes: Cache renewal cycle: 16-byte read access, write-back cycle in write-back buffer: 16-byte
write access
* Neither LRU renewed. LRU is renewed in all other cases.
7.3.6 Coherency of Cache and External Memory
Use software to ensure coherency between the cache and the external memory. When memory
shared by this LSI and another device is mapped in the cache-enabled space, operate the memory-
mapped cache to invalidate and write back as required.
Rev. 3.00 Jun. 18, 2008 Page 193 of 1160
REJ09B0191-0300