SH7206 Datasheet, PDF (877/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 A/D Converter (ADC)
17.4.4 Simultaneous Sampling Operation
With simultaneous sampling, A/D conversion is performed with the input voltages on two
channels (A/D0 and A/D1) sampled at the same time. Simultaneous sampling is valid in single
mode, multi mode, and scan mode. The channels for simultaneous sampling are determined by the
CH[2:0] bits in the A/D control/status register (ADCSR_0 or ADCSR_1). The procedure for
setting simultaneous sampling is to select the operating mode, input channels, and operating clock.
Writing 1 to the DSMP bit in the A/D0, A/D1 control register (ADCR) starts simultaneous
sampling for A/D0 and A/D1. Even though the DSMP bit is changed during A/D conversion, A/D
conversion is not halted. To halt A/D conversion, change the ADST bit. The timing for
simultaneous sampling is the same as the timing for each operating mode.
17.4.5 A/D Converter Activation by External Trigger, MTU2, or MTU2S
The A/D converter can be independently activated by an A/D conversion request from the external
trigger, MTU2, or MTU2S. To activate the A/D converter by the external trigger, MTU2, or
MTU2S, set the A/D trigger enable bits (TRGS[3:0]). After this bit setting has been made, the
ADST bit is automatically set to 1 and A/D conversion is started when an A/D conversion request
from the external trigger, MTU2, or MTU2S occurs. If the TRGS[3:0] bits in both ADCSR_0 and
ADCSR_1 select the same conversion trigger, A/D conversion starts simultaneously on A/D0 and
A/D1. The channel combination is determined by the CH[2:0] bits in ADCSR_0 and ADCSR_1.
The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is
written to the ADST bit by software.
17.4.6 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at the A/D conversion start delay time (t_D) after the ADST bit in ADCSR is set to 1, then
starts conversion. Figure 17.5 shows the A/D conversion timing. Table 17.4 indicates the A/D
conversion time.
As indicated in figure 17.5, the A/D conversion time (t_CONV) includes t_D and the input sampling
time(t_SPL). The length of t_D varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 17.4.
In multi mode and scan mode, the values given in table 17.4 apply to the first conversion. In the
second and subsequent conversions, time is the values given in table 17.5.
Rev. 3.00 Jun. 18, 2008 Page 853 of 1160
REJ09B0191-0300