SH7206 Datasheet, PDF (434/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Overrun 0 at
high level)
DACK
(Active-high)
CPU
1st acceptance
Non sensitive period
DMAC Write
2nd acceptance
3rd acceptance possible
Non sensitive period
CKIO
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
CPU
DMAC Write
1st acceptance
2nd acceptance
3rd acceptance possible
Non sensitive period Non sensitive period
Figure 9.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
when DACK is Split to 4 Due to Idia Cycles
Rev. 3.00 Jun. 18, 2008 Page 410 of 1160
REJ09B0191-0300