SH7206 Datasheet, PDF (173/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Interrupt Controller (INTC)
5.8 Register Banks
This LSI has fifteen register banks used to perform register saving and restoration required in the
interrupt processing at high speed. Figure 5.10 shows the register bank configuration.
Registers
General
registers
Control
registers
System
registers
R0
R1
:
:
R14
R15
SR
GBR
VBR
TBR
MACH
MACL
PR
PC
Register banks
R0
R1
Interrupt generated
:
(save)
:
R14
Bank 0
Bank 1
....
Bank 14
GBR
RESBANK
instruction
(restore)
MACH
MACL
PR
VTO
Bank control registers (interrupt controller)
Bank control register
Bank number register
IBCR
IBNR
Note:
: Banked register
VTO: Vector table address offset
Figure 5.10 Overview of Register Bank Configuration
Rev. 3.00 Jun. 18, 2008 Page 149 of 1160
REJ09B0191-0300