SH7206 Datasheet, PDF (707/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Port Output Enable 2 (POE2)
Initial
Bit
Bit Name Value R/W Description
8
OIE2
0
R/W Output Short Interrupt Enable 2
Enables or disables interrupt requests when the OSF2 bit
in OCSR2 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
7 to 0 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
12.3.5 Input Level Control/Status Register 3 (ICSR3)
ICSR3 is a 16-bit readable/writable register that selects the POE8 pin input mode, controls the
enable/disable of interrupts, and indicates status.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
- POE8F -
- POE8E PIE3
-
-
-
-
-
-
POE8M[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/(W)*¹ R
R R/W*² R/W R
R
R
R
R
R R/W*² R/W*²
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
Initial
Bit
Bit Name Value R/W
15 to 13 —
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jun. 18, 2008 Page 683 of 1160
REJ09B0191-0300