SH7206 Datasheet, PDF (413/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Direct Memory Access Controller (DMAC)
(3) On-Chip Peripheral Module Request
In this mode, the transfer is performed in response to the DMA transfer request signal from an on-
chip peripheral module.
Signals that request DMA transfer from on-chip peripheral modules include transmit FIFO data
empty and receive FIFO data full from the SCIF, transmit data empty and receive data full from
the IIC3, A/D conversion end transfer requests from the A/D converter, input capture/compare
match from the MTU2, and compare match from the CMT.
When a transfer request signal is sent in on-chip peripheral module request mode while DMA
transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, and NMIF = 0), DMA transfer is
performed.
When the transmit FIFO data empty from the SCIF is selected, specify the transfer destination as
the corresponding SCIF transmit FIFO data register. Likewise, when the receive FIFO data full
from the SCIF is selected, specify the transfer source as the corresponding SCIF receive FIFO data
register. When the transmit data empty from IIC3 is selected as the transfer request, the transfer
destination must be ICDRT; when the receive data full from IIC3 is selected as the transfer
request, the transfer source must be ICDRR. When a transfer request is set to the end of A/D
conversion by the A/D converter, the transfer source must be the A/D data register (ADDR). Any
address can be specified for data transfer source and destination when a transfer request is set to an
input capture/compare match from the MTU2 or compare match from the CMT.
Rev. 3.00 Jun. 18, 2008 Page 389 of 1160
REJ09B0191-0300