SH7206 Datasheet, PDF (1000/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 21 On-Chip RAM
21.2 Usage Notes
21.2.1 Page Conflict
When the same page is accessed from different buses simultaneously, a conflict on the page
occurs. Although each access is completed correctly, this kind of conflict degrades the memory
access speed. Therefore, it is advisable to provide software measures to prevent such conflicts as
far as possible. For example, no conflict will arise if different pages are accessed by each bus.
21.2.2 RAME and RAMWE Bits
Before disabling memory operation or write access through the RAME or RAMWE bit, be sure to
read from any address and then write to the same address in each page; otherwise, the last written
data in each page may not be actually written to the RAM.
// For page 0
MOV.L #H'FFF80000,R0
MOV.L @R0,R1
MOV.L R1,@R0
// For page 1
MOV.L #H'FFF88000,R0
MOV.L @R0,R1
MOV.L R1,@R0
// For page 2
MOV.L #H'FFF90000,R0
MOV.L @R0,R1
MOV.L R1,@R0
// For page 3
MOV.L #H'FFF98000,R0
MOV.L @R0,R1
MOV.L R1,@R0
Figure 21.1 Examples of Read/Write before Disabling RAM
Rev. 3.00 Jun. 18, 2008 Page 976 of 1160
REJ09B0191-0300