SH7206 Datasheet, PDF (319/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
(3) Burst Read
A burst read occurs in the following cases with this LSI.
• Access size in reading is larger than data bus width.
• 16-byte transfer in cache miss.
• 16-byte transfer in DMAC
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively 4 times to read 16-byte continuous data from the SDRAM that
is connected to a 32-bit data bus. This access is called the burst read with the burst number 4.
Table 8.14 shows the relationship between the access size and the number of bursts.
Table 8.14 Relationship between Access Size and Number of Bursts
Bus Width
16 bits
32 bits
Access Size
8 bits
16 bits
32 bits
16 bits
8 bits
16 bits
32 bits
16 bits
Number of Bursts
1
1
2
8
1
1
1
4
Figures 8.18 and 8.19 show a timing chart in burst read. In burst read, an ACTV command is
output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA
command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external
clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an
auto-precharge induced by the READA command in the SDRAM. In the Tap cycle, a new
command will not be issued to the same bank. However, access to another CS space or another
bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the WTRP1
and WTRP0 bits in CS3WCR.
Rev. 3.00 Jun. 18, 2008 Page 295 of 1160
REJ09B0191-0300