SH7206 Datasheet, PDF (232/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
8.4.1 Common Control Register (CMNCR)
CMNCR is a 32-bit register that controls the common items for each area. This register is
initialized to H'00001010 by a power-on reset and retains the value by a manual reset and in
software standby mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
- BLOCK DPRTY[1:0]
DMAIW[2:0]
DMA
IWA
-
-
-
HIZ HIZ
MEM CNT
Initial value: 0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
R/W: R
R
R
R R/W R/W R/W R/W R/W R/W R/W R
R
R R/W R/W
Bit
Bit Name
31 to 13 
Initial
Value
All 0
12

1
11
BLOCK
0
10, 9 DPRTY[1:0] 00
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Reserved
This bit is always read as 1. The write value should
always be 1.
R/W Bus Lock
Specifies whether or not the BREQ signal is received.
0: Receives BREQ.
1: Does not receive BREQ.
R/W DMA Burst Transfer Priority
Specify the priority for a refresh request/bus
mastership request during DMA burst transfer.
00: Accepts a refresh request and bus mastership
request during DMA burst transfer.
01: Accepts a refresh request but does not accept a
bus mastership request during DMA burst transfer.
10: Accepts neither a refresh request nor a bus
mastership request during DMA burst transfer.
11: Reserved (setting prohibited)
Rev. 3.00 Jun. 18, 2008 Page 208 of 1160
REJ09B0191-0300