SH7206 Datasheet, PDF (868/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 A/D Converter (ADC)
17.3.3 A/D0, A/D1 Control Register (ADCR)
ADCR is a 16-bit readable/writable register that selects the simultaneous sampling of two
channels.
ADCR is initialized to H'0000 by a power-on reset or in software standby mode or module
standby mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DSMP -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
15
DSMP
14 to 0 
Initial
Value
0
All 0
R/W Description
R/W Simultaneous Sampling Operation Select
Selects A/D0 and A/D1 simultaneous sampling. Starts
simultaneous sampling of two channels when this bit is
set to 1. This bit remains set to 1 during A/D
conversion.
This bit is automatically cleared to 0 when A/D
conversion ends on all selected channels for each
operating mode.
Note: Set ADCSR before setting this bit.
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jun. 18, 2008 Page 844 of 1160
REJ09B0191-0300