SH7206 Datasheet, PDF (239/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
10, 9 BSZ[1:0] 11*
R/W Data Bus Width Specification
Specify the data bus widths of spaces.
00: Reserved (setting prohibited)
01: 8-bit size
10: 16-bit size
11: 32-bit size
For MPX-I/O, selects bus width by address
Notes:
1. If area 5 is specified as MPX-I/O, the bus
width can be specified as 8 bits or 16 bits
by the address according to the SZSEL bit
in CS5WCR by specifying the BSZ[1:0]
bits to 11. The fixed bus width can be
specified as 8 bits or 16 bits
2. The initial data bus width for areas 0 to 8
is specified by external pins. The BSZ[1:0]
bits settings in CS0BCR are ignored but
the bus width settings in CS1BCR to
CS8BCR can be modified.
3. If area 6 is specified as burst MPX-I/O
space, the bus width can be specified as
32 bits only.
4. If area 5 or area 6 is specified as PCMCIA
space, the bus width can be specified as
either 8 bits or 16 bits.
5. If area 2 or area 3 is specified as SDRAM
space, the bus width can be specified as
either 16 bits or 32 bits.
6. If area 0 is specified as clocked
synchronous burst ROM space, the bus
width can be specified as either 16 bits or
32 bits.
8 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: * CSnBCR samples the external pins (MD2 and MD0) that specify the bus width at
power-on reset.
Rev. 3.00 Jun. 18, 2008 Page 215 of 1160
REJ09B0191-0300