SH7206 Datasheet, PDF (15/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

10.3.11 Timer A/D Converter Start Request Cycle Set Registers
(TADCORA_4 and TADCORB_4)...................................................................... 471
10.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA_4 and TADCOBRB_4) ................................................................ 471
10.3.13 Timer Counter (TCNT)......................................................................................... 472
10.3.14 Timer General Register (TGR) ............................................................................. 472
10.3.15 Timer Start Register (TSTR) ................................................................................ 473
10.3.16 Timer Synchronous Register (TSYR)................................................................... 475
10.3.17 Timer Counter Synchronous Start Register (TCSYSTR) ..................................... 477
10.3.18 Timer Read/Write Enable Register (TRWER) ..................................................... 480
10.3.19 Timer Output Master Enable Register (TOER) .................................................... 481
10.3.20 Timer Output Control Register 1 (TOCR1) .......................................................... 482
10.3.21 Timer Output Control Register 2 (TOCR2) .......................................................... 485
10.3.22 Timer Output Level Buffer Register (TOLBR) .................................................... 488
10.3.23 Timer Gate Control Register (TGCR) .................................................................. 489
10.3.24 Timer Subcounter (TCNTS) ................................................................................. 491
10.3.25 Timer Dead Time Data Register (TDDR)............................................................. 492
10.3.26 Timer Cycle Data Register (TCDR) ..................................................................... 492
10.3.27 Timer Cycle Buffer Register (TCBR)................................................................... 493
10.3.28 Timer Interrupt Skipping Set Register (TITCR) ................................................... 493
10.3.29 Timer Interrupt Skipping Counter (TITCNT)....................................................... 495
10.3.30 Timer Buffer Transfer Set Register (TBTER) ...................................................... 496
10.3.31 Timer Dead Time Enable Register (TDER).......................................................... 498
10.3.32 Timer Waveform Control Register (TWCR) ........................................................ 499
10.3.33 Bus Master Interface............................................................................................. 501
10.4 Operation ........................................................................................................................... 502
10.4.1 Basic Functions..................................................................................................... 502
10.4.2 Synchronous Operation......................................................................................... 508
10.4.3 Buffer Operation ................................................................................................... 510
10.4.4 Cascaded Operation .............................................................................................. 514
10.4.5 PWM Modes ......................................................................................................... 519
10.4.6 Phase Counting Mode........................................................................................... 524
10.4.7 Reset-Synchronized PWM Mode.......................................................................... 531
10.4.8 Complementary PWM Mode................................................................................ 534
10.4.9 A/D Converter Start Request Delaying Function.................................................. 579
10.4.10 MTU2–MTU2S Synchronous Operation.............................................................. 583
10.4.11 External Pulse Width Measurement...................................................................... 589
10.4.12 Dead Time Compensation..................................................................................... 590
10.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ....... 593
10.5 Interrupt Sources................................................................................................................ 594
Rev. 3.00 Jun. 18, 2008 Page xv of xxiv