SH7206 Datasheet, PDF (153/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Interrupt Controller (INTC)
PINT interrupt request register (PIRR). The above description also applies to when using high-
level sensing, except for the polarity being reversed. The PINT interrupt exception handling sets
the I3 to I0 bits in SR to the priority level of the PINT interrupt.
When returning from IRQ interrupt exception service routine, execute the RTE instruction after
confirming that the interrupt request has been cleared by the PINT interrupt request register
(PIRR) so as not to accidentally receive the interrupt request again.
5.4.6 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following on-chip peripheral modules:
• A/D converter (ADC)
• Direct memory access controller (DMAC)
• Compare match timer (CMT)
• Bus state controller (BSC)
• Watchdog timer (WDT)
• Multi-function timer pulse unit 2 (MTU2)
• Multi-function timer pulse unit 2S (MTU2S)
• Port output enable 2 (POE2)
• I²C bus interface 3 (IIC3)
• Serial communication interface with FIFO (SCIF)
As every source is assigned a different interrupt vector, the source does not need to be identified in
the exception service routine. A priority level in a range from 0 to 15 can be set for each module
by interrupt priority registers 05 to 14 (IPR05 to IPR14). The on-chip peripheral module interrupt
exception handling sets the I3 to I0 bits in SR to the priority level of the accepted on-chip
peripheral module interrupt.
Rev. 3.00 Jun. 18, 2008 Page 129 of 1160
REJ09B0191-0300