SH7206 Datasheet, PDF (291/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
8.5.2 Normal Space Interface
(1) Basic Timing
For access to a normal space, this LSI uses strobe signal output in consideration of the fact that
mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see
section 8.5.8, SRAM Interface with Byte Selection. Figure 8.3 shows the basic timings of normal
space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for
one cycle to indicate the start of a bus cycle.
CKIO
T1
T2
A25 to A0
CSn
RD/WR
Read
RD
D31 to D0
RD/WR
Write
WEn
D31 to D0
BS
DACKn^*
Note: * The waveform for DACKn is when active low is specified.
Figure 8.3 Normal Space Basic Access Timing (Access Wait 0)
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 32 bits are always
Rev. 3.00 Jun. 18, 2008 Page 267 of 1160
REJ09B0191-0300