SH7206 Datasheet, PDF (132/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Exception Handling
Exception Type
General illegal instruction
Integer division exception
Stack Status
SP
Start address of general
illegal instruction
SR
32 bits
32 bits
SP
Start address of relevant
integer division instruction
SR
32 bits
32 bits
Rev. 3.00 Jun. 18, 2008 Page 108 of 1160
REJ09B0191-0300