SH7206 Datasheet, PDF (19/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

15.5 SCIF Interrupts .................................................................................................................. 786
15.6 Usage Notes ....................................................................................................................... 787
15.6.1 SCFTDR Writing and TDFE Flag ........................................................................ 787
15.6.2 SCFRDR Reading and RDF Flag ......................................................................... 787
15.6.3 Restriction on DMAC Usage ................................................................................ 788
15.6.4 Break Detection and Processing ........................................................................... 788
15.6.5 Sending a Break Signal......................................................................................... 788
15.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 789
Section 16 I²C Bus Interface 3 (IIC3) ................................................................791
16.1 Features.............................................................................................................................. 791
16.2 Input/Output Pins ............................................................................................................... 793
16.3 Register Descriptions ......................................................................................................... 794
16.3.1 I²C Bus Control Register 1 (ICCR1)..................................................................... 795
16.3.2 I²C Bus Control Register 2 (ICCR2)..................................................................... 798
16.3.3 I²C Bus Mode Register (ICMR)............................................................................ 800
16.3.4 I²C Bus Interrupt Enable Register (ICIER) ........................................................... 802
16.3.5 I²C Bus Status Register (ICSR)............................................................................. 804
16.3.6 Slave Address Register (SAR).............................................................................. 807
16.3.7 I²C Bus Transmit Data Register (ICDRT)............................................................. 807
16.3.8 I²C Bus Receive Data Register (ICDRR).............................................................. 808
16.3.9 I²C Bus Shift Register (ICDRS)............................................................................ 808
16.3.10 NF2CYC Register (NF2CYC) .............................................................................. 809
16.4 Operation ........................................................................................................................... 810
16.4.1 I²C Bus Format...................................................................................................... 810
16.4.2 Master Transmit Operation ................................................................................... 811
16.4.3 Master Receive Operation..................................................................................... 813
16.4.4 Slave Transmit Operation ..................................................................................... 815
16.4.5 Slave Receive Operation....................................................................................... 818
16.4.6 Clocked Synchronous Serial Format..................................................................... 820
16.4.7 Noise Filter ........................................................................................................... 824
16.4.8 Example of Use..................................................................................................... 825
16.5 Interrupt Requests .............................................................................................................. 829
16.6 Bit Synchronous Circuit..................................................................................................... 830
16.7 Usage Notes ....................................................................................................................... 833
16.7.1 Note on Issue of Stop/Start Conditions................................................................. 833
16.7.2 Settings for Multi-Master Operation..................................................................... 833
16.7.3 Note on Master Receive Mode.............................................................................. 833
16.7.4 Note on Setting ACKBT in Master Receive Mode............................................... 834
16.7.5 Note on the States of Bits MST and TRN when Arbitration is Lost..................... 834
Rev. 3.00 Jun. 18, 2008 Page xix of xxiv