SH7206 Datasheet, PDF (770/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
2
PER
0
R
Parity Error Indication
Indicates a parity error in the data read from the next
receive FIFO data register (SCFRDR) in
asynchronous mode.
0: No receive parity error occurred in the next data
read from SCFRDR
[Clearing conditions]
• PER is cleared to 0 when the chip undergoes a
power-on reset
• PER is cleared to 0 when no parity error is present
in the next data read from SCFRDR
1: A receive parity error occurred in the next data read
from SCFRDR
[Setting condition]
• PER is set to 1 when a parity error is present in
the next data read from SCFRDR
Rev. 3.00 Jun. 18, 2008 Page 746 of 1160
REJ09B0191-0300