SH7206 Datasheet, PDF (996/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 I/O Ports
20.7.2 Port F Data Register (PFDR)
PFDR is a 16-bit read-only register that stores port F data. Bits PF7DR to PF0DR correspond to
pins PF7/AN7/DA1 to PF0/AN0, respectively. The general input function of pins PF7 to PF0 is
enabled only when the A/D converter and D/A converter are halted.
Even if a value is written to PFDR, that value is not written into PFDR, and it does not affect the
pin state. If PFDR is read, the pin state, not the register value, is returned directly. However,
PFDR should not be read when the A/D converter and D/A converter are operating. Table 20.12
summarizes PFDR read/write operations.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
DR DR DR DR DR DR DR DR
Initial value: 0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Note: * Depends on the external pin state.
Initial
Bit
Bit Name Value R/W
15 to 8 
All 0
R
7
PF7DR Pin state R
6
PF6DR Pin state R
5
PF5DR Pin state R
4
PF4DR Pin state R
3
PF3DR Pin state R
2
PF2DR Pin state R
1
PF1DR Pin state R
0
PF0DR Pin state R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
See table 20.12
Rev. 3.00 Jun. 18, 2008 Page 972 of 1160
REJ09B0191-0300