SH7206 Datasheet, PDF (203/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Cache
Section 7 Cache
7.1 Features
• Capacity
Instruction cache: 8 Kbytes
Operand cache: 8 Kbytes
• Structure: Instructions/data separated, 4-way set associative
• Way lock function (only for operand cache): Way 2 and way 3 are lockable
• Line size: 16 bytes
• Number of entries: 128 entries/way
• Write system: Write-back/write-through selectable
• Replacement method: Least-recently-used (LRU) algorithm
7.1.1 Cache Structure
The cache separates data and instructions and uses a 4-way set associative system. It is composed
of four ways (banks), each of which is divided into an address section and a data section.
Each of the address and data sections is divided into 128 entries per way. The data section of the
entry is called a line. Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 2
Kbytes (16 bytes × 128 entries), with a total of 8 Kbytes in the cache as a whole (4 ways). Figure
7.1 shows the operand cache structure. The instruction cache structure is the same as the operand
cache structure except for not having the U bit.
Rev. 3.00 Jun. 18, 2008 Page 179 of 1160
REJ09B0191-0300