SH7206 Datasheet, PDF (1006/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 22 Power-Down Modes
22.2.3 Standby Control Register 3 (STBCR3)
STBCR3 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. STBCR3 is initialized to H'7E by a power-on reset but retains its previous value by a
manual reset or in software standby mode. Only byte access is valid.
Note: See section 22.4, Usage Notes, when writing data to this register.
Bit: 7
6
5
4
3
2
1
0
HIZ
MSTP MSTP MSTP MSTP MSTP MSTP
36
35
34
33
32
31
-
Initial value: 0
1
1
1
1
1
1
0
R/W: R/W R/W R/W R/W R/W R/W R/W R
Initial
Bit
Bit Name Value R/W Description
7
HIZ
0
R/W Port High Impedance
Selects whether the state of a specified pin is
retained or the pin is placed in the high-impedance
state in software standby mode. See appendix A, Pin
States, to determine the pin to which this control is
applied.
Do not set this bit when the TME bit of WTSCR of the
WDT is 1. When setting the output pin to the high-
impedance state, set the HIZ bit with the TME bit
being 0.
0: The pin state is held in software standby mode.
1: The pin state is set to the high-impedance state in
software standby mode.
6
MSTP36 1
R/W Module Stop 36
When the MSTP36 bit is set to 1, the supply of the
clock to the MTU2S is halted.
0: MTU2S runs.
1: Clock supply to MTU2S halted.
5
MSTP35 1
R/W Module Stop 35
When the MSTP35 bit is set to 1, the supply of the
clock to the MTU2 is halted.
0: MTU2 runs.
1: Clock supply to MTU2 halted.
Rev. 3.00 Jun. 18, 2008 Page 982 of 1160
REJ09B0191-0300