SH7206 Datasheet, PDF (95/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 3 Clock Pulse Generator (CPG)
The clock pulse generator blocks function as follows:
(1) PLL Circuit 1
PLL circuit 1 multiplies the input clock frequency from the CKIO pin by 1, 2, 3, 4, 6, or 8. The
multiplication rate is set by the frequency control register. When this is done, the phase of the
rising edge of the internal clock is controlled so that it will agree with the phase of the rising edge
of the CKIO pin.
(2) PLL Circuit 2
PLL circuit 2 multiplies the input clock frequency from the crystal oscillator or EXTAL pin by 4.
The multiplication rate is fixed according to the clock operating mode. The clock operating mode
is specified by the MD_CLK0 and MD_CLK2 pins. For details on the clock operating mode, see
table 3.2.
(3) Crystal Oscillator
The crystal oscillator is an oscillation circuit in which a crystal resonator is connected to the
XTAL pin or EXTAL pin. This can be used according to the clock operating mode.
(4) Divider 1
Divider 1 generates a clock signal at the operating frequency used by the internal or peripheral
clock. The operating frequency can be 1, 1/2, 1/3, 1/4, 1/6, 1/8, or 1/12 times the output frequency
of PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin. The division
ratio is set in the frequency control register (FRQCR).
(5) Divider 2
Divider 2 generates a clock signal at the operating frequency used by the MTU2S. The operating
frequency of the MTU2S can be 1, 1/2, 1/3, or 1/4 times the output frequency of PLL circuit 1,
while it is an integer multiple of the peripheral clock (Pφ). The division ratio is set by the MTU
clock frequency control register.
(6) Clock Frequency Control Circuit
The clock frequency control circuit controls the clock frequency using the MD_CLK0 and
MD_CLK2 pins and the frequency control register (FRQCR).
Rev. 3.00 Jun. 18, 2008 Page 71 of 1160
REJ09B0191-0300