SH7206 Datasheet, PDF (487/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
0
CMFW5
0
R/(W)*¹ Compare Match/Input Capture Flag W5
Status flag that indicates the occurrence of TGRW_5
input capture or compare match.
[Clearing condition]
• When 0 is written to CMFW5 after reading CMFW5 =
1
[Setting conditions]
• When TCNTW_5 = TGRW_5 and TGRW_5 is
functioning as output compare register
• When TCNTW_5 value is transferred to TGRW_5 by
input capture signal and TGRW_5 is functioning as
input capture register
• When TCNTW_5 value is transferred to TGRW_5 and
TGRW_5 is functioning as a register for measuring
the pulse width of the external input signal. *²
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Timing for transfer is set by the IOC bit in the timer I/O control register U_5/V_5/W_5
(TIORU_5/V_5/W_5).
Rev. 3.00 Jun. 18, 2008 Page 463 of 1160
REJ09B0191-0300