SH7206 Datasheet, PDF (414/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Direct Memory Access Controller (DMAC)
Table 9.8 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
CHCR DMARS DMA Transfer
Request
RS[3:0] MID RID Source
DMA Transfer
Request Signal
Transfer
Source
Transfer Bus
Destination Mode
1000
100000 01 SCIF_0 transmit TXI0 (transmit FIFO data empty) Any
SCFTDR_0 Cycle
10 SCIF_0 receive RXI0 (receive FIFO data full)
SCFRDR_0 Any
steal
100001 01 SCIF_1 transmit TXI1 (transmit FIFO data empty) Any
SCFTDR_1
10 SCIF_1 receive RXI1 (receive FIFO data full)
SCFRDR_1 Any
100010 01 SCIF_2 transmit TXI2 (transmit FIFO data empty) Any
SCFTDR_2
10 SCIF_2 receive RXI2 (receive FIFO data full)
SCFRDR_2 Any
100011 01 SCIF_3 transmit TXI3 (transmit FIFO data empty) Any
SCFTDR_3
10 SCIF_3 receive RXI3 (receive FIFO data full)
SCFRDR_3 Any
101000 01 IIC3 transmit
10 IIC3 receive
TXI (transmit data empty)
RXI (receive data full)
Any
ICDRR
ICDRT
Any
Cycle
steal
101100 11 A/D converter_0 ADI0 (A/D conversion end)
101101 11 A/D converter_1 ADI1 (A/D conversion end)
ADDR0 Any
ADDR1 Any
Cycle
steal
111000 11 MTU2_0
TGI0A (input capture/compare Any
Any
Cycle
match)
steal or
111001 11 MTU2_1
TGI1A (input capture/compare Any
Any
burst
match)
111010 11 MTU2_2
TGI2A (input capture/compare Any
Any
match)
111011 11 MTU2_3
TGI3A (input capture/compare Any
Any
match)
111100 11 MTU2_4
TGI4A (input capture/compare Any
Any
match)
111110 11 CMT_0
111111 11 CMT_1
CMI0 (compare match)
CMI1 (compare match)
Any
Any
Cycle
Any
Any
steal or
burst
Rev. 3.00 Jun. 18, 2008 Page 390 of 1160
REJ09B0191-0300