SH7206 Datasheet, PDF (705/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Port Output Enable 2 (POE2)
Initial
Bit Bit Name Value R/W Description
5, 4 POE6M[1:0] 00
R/W*² POE6 Mode
These bits select the input mode of the POE6 pin.
00: Accept request on falling edge of POE6 input
01: Accept request when POE6 input has been sampled
for 16 Pφ/8 clock pulses and all are at a low level.
10: Accept request when POE6 input has been sampled
for 16 Pφ/16 clock pulses and all are at a low level.
11: Accept request when POE6 input has been sampled
for 16 Pφ/128 clock pulses and all are at a low level.
3, 2 POE5M[1:0] 00
R/W*² POE5 Mode
These bits select the input mode of the POE5 pin.
00: Accept request on falling edge of POE5 input
01: Accept request when POE5 input has been sampled
for 16 Pφ/8 clock pulses and all are at a low level.
10: Accept request when POE5 input has been sampled
for 16 Pφ/16 clock pulses and all are at a low level.
11: Accept request when POE5 input has been sampled
for 16 Pφ/128 clock pulses and all are at a low level.
1, 0 POE4M[1:0] 00
R/W*² POE4 Mode
These bits select the input mode of the POE4 pin.
00: Accept request on falling edge of POE4 input
01: Accept request when POE4 input has been sampled
for 16 Pφ/8 clock pulses and all are at a low level.
10: Accept request when POE4 input has been sampled
for 16 Pφ/16 clock pulses and all are at a low level.
11: Accept request when POE4 input has been sampled
for 16 Pφ/128 clock pulses and all are at a low level.
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
Rev. 3.00 Jun. 18, 2008 Page 681 of 1160
REJ09B0191-0300