SH7206 Datasheet, PDF (68/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 2 CPU
Addressing
Mode
Immediate
Instruction
Format
Effective Address Calculation
Equation
#imm:20 The 20-bit immediate data (imm) for the MOVI20 —
instruction is sign-extended.
31
19
0
Sign-
extended
imm (20 bits)
The 20-bit immediate data (imm) for the MOVI20S —
instruction is shifted by eight bits to the left, the
upper bits are sign-extended, and the lower bits are
padded with zero.
31 27
8
0
imm (20 bits) 00000000
#imm:8
#imm:8
#imm:8
#imm:3
Sign-extended
The 8-bit immediate data (imm) for the TST, AND, —
OR, and XOR instructions is zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD, —
and CMP/EQ instructions is sign-extended.
The 8-bit immediate data (imm) for the TRAPA
—
instruction is zero-extended and then quadrupled.
The 3-bit immediate data (imm) for the BAND, BOR, —
BXOR, BST, BLD, BSET, and BCLR instructions
indicates the target bit location.
Rev. 3.00 Jun. 18, 2008 Page 44 of 1160
REJ09B0191-0300