SH7206 Datasheet, PDF (35/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
Classification
Interrupts
Address bus
Data bus
Bus control
Symbol
I/O
NMI
I
IRQ7 to IRQ0 I
PINT7 to PINT0 I
IRQOUT
O
A25 to A0
O
D31 to D0
I/O
CS8 to CS0
O
RD
O
RD/WR
O
BS
O
AH
O
FRAME
O
WAIT
I
WE0
O
Name
Function
Non-maskable Non-maskable interrupt request pin.
interrupt
Fix it high when not in use.
Interrupt requests Maskable interrupt request pins.
7 to 0
Level-input or edge-input detection
can be selected. When the edge-
input detection is selected, the rising
edge, falling edge, or both edges can
also be selected.
Interrupt requests Maskable interrupt request pins.
7 to 0
Only level-input detection can be
selected.
Interrupt request
output
Indicates that an interrupt has
occurred, enabling external devices
to be informed of an interrupt
occurrence even while the bus
mastership is released.
Address bus
Outputs addresses.
Data bus
Bidirectional data bus.
Chip select 8 to 0 Chip-select signals for external
memory or devices.
Read
Indicates that data is read from an
external device.
Read/write
Read/write signal.
Bus start
Bus-cycle start signal.
Address hold
FRAME signal
Address hold timing signal for the
device that uses the address/data-
multiplexed bus.
Connected to the FRAME signal in
the burst MPX-I/O interface.
Wait
Input signal for inserting a wait cycle
into the bus cycles during access to
the external space.
Byte select
Indicates a write access to bits 7 to 0
of data of external memory or
device.
Rev. 3.00 Jun. 18, 2008 Page 11 of 1160
REJ09B0191-0300