SH7206 Datasheet, PDF (172/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Interrupt Controller (INTC)
2 Icyc + 3 Bcyc + 1 Pcyc
2 Icyc + 17(m4)
1 Icyc + m1 + m2 + 2(m4)
IRQ
RESBANK instruction
m4 m4
m1 m2 m3
F D E M M M ... M M M W
Instruction (instruction replacing
interrupt exception handling)
D E E M M M ^...
First instruction in interrupt
exception service routine
F ^... D
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
m4: Restoration of banked registers
Interrupt acceptance
Figure 5.9 Example of Pipeline Operation when Interrupt is Accepted during RESBANK
Instruction Execution (Register Banking with Register Bank Overflow)
Rev. 3.00 Jun. 18, 2008 Page 148 of 1160
REJ09B0191-0300