SH7206 Datasheet, PDF (808/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
In serial reception, the SCIF operates as described below.
1. The SCIF synchronizes with serial clock input or output and starts the reception.
2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the
data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this
check is passed, the RDF flag is set to 1 and the SCIF stores the received data in SCFRDR. If
the check is not passed (overrun error is detected), further reception is prevented.
3. After setting RDF to 1, if the receive FIFO data full interrupt enable bit (RIE) is set to 1 in
SCSCR, the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and
the receive-data-full interrupt enable bit (RIE) or the receive error interrupt enable bit (REIE)
in SCSCR is also set to 1, the SCIF requests a break interrupt (BRI).
Figure 15.17 shows an example of SCIF receive operation.
Serial clock
Serial data
RDF
ORER
Bit 7
LSB
Bit 0
MSB
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RXI
interrupt
request
Data read from SCFRDR and
RDF flag cleared to 0 by RXI
interrupt handler
One frame
RXI
interrupt
request
Figure 15.17 Example of SCIF Receive Operation
BRI interrupt request
by overrun error
Rev. 3.00 Jun. 18, 2008 Page 784 of 1160
REJ09B0191-0300