SH7206 Datasheet, PDF (311/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
Table 8.9 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (2)-2
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 bits) 01 (12 bits)
10 (10 bits)
Output Pin of Row Address Column Address
This LSI
Output Cycle Output Cycle
SDRAM Pin
Function
A17
A27
A17
Unused
A16
A26
A16
A15
A25*²*³
A25*²*³
A13 (BA1)
Specifies bank
A14
A24*²
A24*²
A12 (BA0)
A13
A23
A12
A22
A13
L/H*¹
A11
A10/AP
Address
Specifies
address/precharge
A11
A21
A11
A9
Address
A10
A20
A10
A8
A9
A19
A9
A7
A8
A18
A8
A6
A7
A17
A7
A5
A6
A16
A6
A4
A5
A15
A5
A3
A4
A14
A4
A2
A3
A13
A3
A1
A2
A12
A2
A0
A1
A11
A1
Unused
A0
A10
A0
Example of connected memory
512-Mbit product (4 Mwords × 32 bits × 4 banks, column 10-bit product): 1
256-Mbit product (4 Mwords × 16 bits × 4 banks, column 10-bit product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification.
3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU
is not asserted.
Rev. 3.00 Jun. 18, 2008 Page 287 of 1160
REJ09B0191-0300