SH7206 Datasheet, PDF (890/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 D/A Converter (DAC)
18.3.2 D/A Control Register (DACR)
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.
DACR is initialized to H'1F by a power-on reset or in module standby mode.
Bit: 7
6
5
4
3
2
1
0
DAOE1 DAOE0 DAE
-
-
-
-
-
Initial value: 0
0
0
1
1
1
1
1
R/W: R/W R/W R/W -
-
-
-
-
Initial
Bit
Bit Name Value
7
DAOE1 0
6
DAOE0 0
5
DAE
0
4 to 0 
All 1
R/W
R/W
R/W
R/W

Description
D/A Output Enable 1
Controls D/A conversion and analog output for channel 1.
0: Analog output of channel 1 (DA1) is disabled
1: D/A conversion of channel 1 is enabled. Analog output
of channel 1 (DA1) is enabled.
D/A Output Enable 0
Controls D/A conversion and analog output for channel 0.
0: Analog output of channel 0 (DA0) is disabled
1: D/A conversion of channel 0 is enabled. Analog output
of channel 0 (DA0) is enabled.
D/A Enable
Used together with the DAOE0 and DAOE1 bits to control
D/A conversion. Output of conversion results is always
controlled by the DAOE0 and DAOE1 bits. For details,
see table 18.3.
0: D/A conversion for channels 0 and 1 is controlled
independently
1: D/A conversion for channels 0 and 1 is controlled
together
Reserved
These bits are always read as 1 and cannot be modified.
Rev. 3.00 Jun. 18, 2008 Page 866 of 1160
REJ09B0191-0300