SH7206 Datasheet, PDF (1165/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Item
Page Revision (See Manual for Details)
8.4.3 CSn Space Wait Control
Register (CSnWCR) (n = 0 to 8)
(1) Normal Space, SRAM with
Byte Selection, MPX-I/O
216
Table amended.
Bit
21, 20
20
17, 16
Bit Name

Initial
Value
All 0
BAS*
0
*
All 0
R/W
R/W
R/W
R/W
Description
Reserved
Clear these bits to 0 when the interface for normal
space or SRAM with byte selection is used.
Byte Access Selection when SRAM with Byte
Selection is Used
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read/write timing and
asserts the RD/WR signal during the write access cycle.
1: Asserts the WEn signal during the read/write access
cycle and asserts the RD/WR signal at the write
timing.
Reserved
Clear these bits to 0 when the interface for normal space
or SRAM with byte selection is used.
8.5.6 SDRAM Interface
289
Table 8.11 Relationship between
BSZ[1:0], A2/3ROW[1:0],
A2/3COL[1:0], and Address
Multiplex Output (4)-1
Table amended.
BSZ
[1:0]
10 (16 bits)
Output Pin of
This LSI
A13
A12
Setting
A2/3
ROW
[1:0]
00 (11 bits)
Row Address
Output Cycle
A21
A20*²
A2/3
COL
[1:0]
00 (8 bits)
Column Address
Output Cycle
A21
SDRAM Pin
A12(BA1)
A20*²
A11(BA )
Function
Unused
Specifies bank
(8) Refreshing
(b) Self-Refreshing
(12) Power-On Sequence
312 Description amended.
… Note that the necessary signals such as CKE must
be driven even in standby state by setting the HIZCNT
bit in CMNCR to 1.
When the multiplication rate for the PLL circuit is
changed, the CKIO output will become unstable or will
be fixed low. For details on the CKIO output, see
section 3, Clock Pulse Generator (CPG). The contents
of SDRAM can be retained by placing the SDRAM in
the self-refresh state before changing the multiplication
rate.
The self-refresh state is not …
317 Description amended.
In order to use SDRAM, mode setting must first be
made for SDRAM after the pose interval specified for
the SDRAM to be used after powering on. The pose
interval should be obtained by a power-on reset
generating circuit or software.
Rev. 3.00 Jun. 18, 2008 Page 1141 of 1160
REJ09B0191-0300