SH7206 Datasheet, PDF (93/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 3 Clock Pulse Generator (CPG)
Section 3 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock
(Pφ), a bus clock (Bφ), and an MTU clock (Mφ). The CPG consists of a crystal oscillator, PLL
circuits, and divider circuits.
3.1 Features
• Two clock operating modes
The mode is selected from among the two clock operating modes by the selection of the
following three conditions: the frequency-divisor in use, whether the PLLs are on or off, and
whether the internal crystal resonator or the input on the external clock-signal line is used.
• Four clocks generated independently
An internal clock (Iφ) for the CPU and cache; a peripheral clock (Pφ) for the on-chip
peripheral modules; a bus clock (Bφ = CKIO) for the external bus interface; an MTU clock
(Mφ) for the MTU2S module.
• Frequency change function
Internal and peripheral clock frequencies can be changed independently using the PLL (phase
locked loop) circuits and divider circuits within the CPG. Frequencies are changed by software
using frequency control register (FRQCR) settings.
• Power-down mode control
The clock can be stopped for sleep mode and software standby mode, and specific modules can
be stopped using the module standby function. For details on clock control in the power-down
modes, see section 22, Power-Down Modes.
Rev. 3.00 Jun. 18, 2008 Page 69 of 1160
REJ09B0191-0300